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High Level Synthesis (or Behavioural Synthesis) is automatic compilation (translation) from a description which is relatively easy to write and read to a representation that can be automatically implemented. The most common synthesis today compiles from a register transfer level language (RTL) to a netlist of existing design fragments (cells, gates, CLBs) in an ASIC/FPGA technology. High Level ... [MORE]
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Daniel Gajski
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Well known researcher.
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Integrated Embedded Systems Automation Group
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Conducts design and design automation research projects including high level synthesis, reconfigurable designs and architectures and system modelling. Includes project descriptions, papers and tools. From University of California, Irvine.
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Visual Architect
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Vendor description of an application-specific, high-level behavioral synthesis tool to assist in the development of SoC products.
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